MC74HC4060AD

Output Type :
Package / Case : SOIC-16
Number of Circuits : 1
Maximum Operating Temperature : + 125 C
Minimum Operating Temperature : - 55 C
Logic Family : 74HC
Logic Type : CMOS
Packaging : Tube
Counter Type : Binary
Counting Sequence : Up
Number of Input Lines : 1
Propagation Delay Time : 500 ns, 350 ns, 250 ns, 200 ns


Features:

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 390 FETs or 97.5 Equivalent Gates


Pinout




Specifications

 

Symbol	Parameter	Value	Unit
vcc	DC Supply Voltage (Referenced to GND)	0.5 to +7.0	V
VIN	DC Input Voltage (Referenced to GND)	0.5 to VCC + 0.5	V
VOUT	DC Output Voltage (Referenced to GND)	0.5 to VCC + 0.5	V
LIN	DC Input Current, per Pin	±20	mA
IOUT	DC Onput Current, per Pin	±25	mA
ICC	DC Supply Current Per Supply Pin	±50	mA
PD	Power dissipation in still air piastic DIP SOIC package	750 500 450	mW
TSTG	Storage Temperature	65 to +150	°C
TL	Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)	260	°C

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating - Plastic DIP: 10 mW/
C from 65
to 125
C
Ceramic DIP: 10 mW/
C from 100
to 125
C
SOIC Package: 7 mW/
C from 65
to 125
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).


Description

The MC74C4060A is identical in pinout to the standard CMOS MC14060B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

MC74HC4060AD consists of 14 masterslave flipflops and an oscillator with a frequency that is controlled either by a crystal or by an RC circuit connected externally. The output of each flipflop MC74HC4060AD feeds the next and the frequency at each output is half of that of the preceding one. The state of the counter advances on the negativegoing edge of the Osc In. The activehigh Reset is asynchronous and disables the oscillator to allow very low power consumption during standby operation.

State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals of MC74HC4060AD are subject to decoding spikes and may have to be gated with Osc Out 2 of the HC4060A.