MC74HC4020AD

Output Type :
Package / Case : SOIC-16
Number of Circuits : 1
Maximum Operating Temperature : + 125 C
Minimum Operating Temperature : - 55 C
Logic Family : 74HC
Logic Type : CMOS
Packaging : Tube
Counter Type : Binary
Counting Sequence : Up
Number of Input Lines : 1
Propagation Delay Time : 96 ns, 63 ns, 31 ns, 25 ns


Features:

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent


Pinout




Specifications

 

Symbol	Parameter	Value	Unit
vcc	DC Supply Voltage (Referenced to GND)	0.5 to +7.0	V
VIN	DC Input Voltage (Referenced to GND)	0.5 to VCC + 0.5	V
VOUT	DC Output Voltage (Referenced to GND)	0.5 to VCC + 0.5	V
LIN	DC Input Current, per Pin	±20	mA
IOUT	DC Onput Current, per Pin	±35	mA
ICC	DC Supply Current Per Supply Pin	±75	mA
PD	Power dissipation in still air piastic DIP SOIC package	750 500 450	mW
TSTG	Storage Temperature	65 to +150	°C
TL	Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)	260	°C

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
?Derating - Plastic DIP: 10 mW/ from 65to 125
Ceramic DIP: 10 mW/ from 100 to 125
SOIC Package: 7 mW/ from 65 to 125
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).


Description

The MC74C4020A is identical in pinout to the standard CMOS MC14020B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

MC74HC4020AD consists of 14 masterslave flipflops with 12 stages brought out to pins. The output of each flipflop feeds the next and the frequency at each output is half of that of the preceding one. Reset is asynchronous and activehigh.

State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals of MC74HC4020AD are subject to decoding spikes and may have to be gated with the Clock of the HC4020A for some designs.