MC74HC373A

Features:

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates


Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	0.5 to +7.0	V
Vin	DC Input Voltage (Referenced to GND)	0.5 to VCC +0.5	V
Vout	DC Output Voltage (Referenced to GND)	0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin	± 20	mA
Iout	DC Output Current, per Pin	± 35	mA
ICC	DC Supply Current, VCC and GND Pins	± 75	mA
PD	Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† SSop or Tssop package†	750 500 450	mW
Tstg	Storage Temperature	65 to + 150
TL	Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP)	260 300

*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation
  should be restricted to the Recommended Operating Conditions.
  †Derating - Plastic DIP: 10 mW/ from 65 ° to 125
  Ceramic DIP: 10 mW/ from 100 ° to 125
  SOIC Package: 7 mW/ from 65 ° to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

This device contains protection circuitry to guard against damage due to high static voltages or electric fields.However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V_in and V_out should be constrained to the range GND (V_in or V_out) V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V_CC). Unused outputs must be left open.


Description

The MC54/74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

These latches of MC74HC373A appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state. Thus, data may be latched even when the outputs are not enabled.

The HC373A is identical in function to the HC573A which has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.

The HC373A is the noninverting version of the HC533A.