PinoutDescriptionThe MC74F544 contains two sets of eight D-type latches, with separate input and controls for each set. For data of MC74F544flow from A to B, for example, the A-to-B Enable (EAB) input must be LOW in order to enter data from A0A7 or take data from B0B7, as indicated in the Function...
MC74F544: PinoutDescriptionThe MC74F544 contains two sets of eight D-type latches, with separate input and controls for each set. For data of MC74F544flow from A to B, for example, the A-to-B Enable (EAB) inp...
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Features: Operating range: 38 to 47 Gb/s (min.) (note)Signal regeneration with full-rate clock sig...
The MC74F544 contains two sets of eight D-type latches, with separate input and controls for each set. For data of MC74F544flow from A to B, for example, the A-to-B Enable (EAB) input must be LOW in order to enter data from A0A7 or take data from B0B7, as indicated in the Function Table. WithEAB LOW, a LOW signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. WithEAB and OEAB both LOW, the 3-State B output buffers of MC74F544 are active and reflect the inverted data present at the output of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs.