MC74F283

The MC54/74F283 high-speed 4-bit binary full adder with internal carry lookahead, accepts two 4-bit binary words (A₀A₃, B₀B₃) and a Carry input (C₀). It generates the binary Sum outputs (S₀S₃) and the Carry output (C₄) from the most significant bit. The F283 will operate with either active-HIGH oractive-LOW operands (positive or negative logic).

The F283 adds two 4-bit binary words (A plus B) plus the incoming carry C₀. The binary sum of MC74F283 appears on the Sum (S₀S₃) and outgoing carry (C₄) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two.

2⁰ (A₀ + B₀ + C₀) + 2¹ (A₁ + B₁) + 2² (A₂ + B₂) + 2³ (A₃ + B₃) = S₀ + 2S₁ + 4S₂ + 8S₃ + 16C₄
Where (+) = plus

Interchanging inputs of equal weight does not affect the operation.Thus C₀, A₀, B₀ can be arbitrarily assigned to pins 5, 6 and 7. Due to the symmetry of the binary add function, the F283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure A. Note that if C₀ is not used it must be tied LOW for active-HIGH logic or tied HIGH for active-LOW logic.

Due to pin limitations, the intermediate carries of the F283 are not brought out for use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure B shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A₃, B₃) LOW makes S₃ dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure C shows a way of dividing the F283 into a 2-bit and a 1-bit adder. The third stage adder (A₂, B₂, S₂) is used merely as a means of getting a carry (C₁₀) signal into the fourth stage (via A₂ and B₂) and bringing out the carry from the second stage on S₂. Note that as long as A₂ and B₂ are the same, whether HIGH or LOW, they do not influence S₂. Similarly, when A₂ and B₂ are the same the carry into the third stage does not influence the carry out of the third stage. Figure D shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S₀, S₁ and S₂ present a binary number equal to the number of inputs I₁I₅ that are true. Figure E shows one method of implementing a 5-input majority gate. When three or more of the inputs I₁I₅ are true, the output M₅ is true.