MC74F112

    The MC74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs.  Synchronous state changes are initiated by the falling edge of the clock.  Triggering of MC74F112 occurs at a voltage level of the clock and is not directly related to the transition time.  The J and K inputs can change when the clock is in either state without affecting the flip-flop MC74F112, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock.  A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively.  Simultaneous LOW signals onSD and CD force both Q and Q HIGH.