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MC74C4060A

Features: Output Drive Capability: 10 LSTTL LoadsOutputs Directly Interface to CMOS, NMOS, and TTLOperating Voltage Range: 2 to 6 VLow Input Current: 1 AHigh Noise Immunity Characteristic of CMOS DevicesIn Compliance With JEDEC Standard No. 7A RequirementsChip Complexity: 390 FETs or 97.5 Equivale...

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MC74C4060A: Features: Output Drive Capability: 10 LSTTL LoadsOutputs Directly Interface to CMOS, NMOS, and TTLOperating Voltage Range: 2 to 6 VLow Input Current: 1 AHigh Noise Immunity Characteristic of CMOS De...

MC74C4060A Data Sheet

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Part Number:
MC74C4060A
Supply Ability:
5000

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Product Details

Description



Features:

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 390 FETs or 97.5 Equivalent Gates


Pinout

Connection Diagram


Specifications


Symbol
Parameter
Value
Unit

VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V

Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V

Vout		 DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V

Iin
DC Input Current, per Pin
±20
mA

Iout
DC Output Current, per Pin
±25
mA

ICC
DC Supply Current, VCC and GND Pins
±50
mA

PD

Power Dissipation in Still Air Plastic DIP+
SOIC Package+
TSSOP Package+

750
500
450
mW
Tstg Storage Temperature Range 65 to + 150
TL TLLead Temperature, 1 mm from Case for 10 SecondsC
Plastic DIP, SOIC or TSSOP Package
260
 


Description

The MC74C4060A is identical in pinout to the standard CMOSMC14060B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

MC74C4060A consists of 14 masterslave flipflops and an oscillator with a frequency that is controlled either by a crystal or by an RC circuit connected externally. The output of each flipflop feeds the next and the frequency at each output of MC74C4060A is half of that of the preceding one. The state of the counter advances on the negativegoing edge of the Osc In. The activehigh Reset is asynchronous and disables the oscillator to allow very low power consumption during standby operation.

State changes of the Q outputs MC74C4060A do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with Osc Out 2 of the HC4060A.




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