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MC74AC377

Features: • Ideal for Addressable Register Applications• Clock Enable for Address and Data Synchronization Applications• Eight Edge-Triggered D Flip-Flops• Buffered Common Clock• Outputs Source/Sink 24 mA• See MC74AC273 for Master Reset Version• See MC74AC...

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SeekIC No. : 004416669 Detail

MC74AC377: Features: • Ideal for Addressable Register Applications• Clock Enable for Address and Data Synchronization Applications• Eight Edge-Triggered D Flip-Flops• Buffered Common Cl...

MC74AC377 Data Sheet

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Part Number:
MC74AC377
Supply Ability:
5000

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Upload time: 2024/11/27

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Product Details

Description



Features:

• Ideal for Addressable Register Applications
• Clock Enable for Address and Data Synchronization Applications
• Eight Edge-Triggered D Flip-Flops
• Buffered Common Clock
• Outputs Source/Sink 24 mA
• See MC74AC273 for Master Reset Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• 'ACT377 Has TTL Compatible Inputs


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC
 DC Supply Voltage (Referenced to GND)
0.5 to +7.0
V
Vin
 DC Input Voltage (Referenced to GND)
0.5 to VCC +0.5
V
Vout
 DC Output Voltage (Referenced to GND)
0.5 to VCC +0.5
V
Iin
 DC Input Current, per Pin
±20
mA
Iout
 DC Output Sink/Source Current, per Pin
±50
mA
ICC
 DC VCC or GND Current per Output Pin
±50
mA
Tstg
 Storage Temperature
65 to +150
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation
   should be restricted to the Recommended Operating Conditions.


Description

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

The register MC74AC377 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.




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