MC68LC302

The features of the LC302 are as follows. The items in bold face type show major differencesfrom the MC68302, although a complete list of differences is given in 1.4 LC302 Differences.
• On-Chip Static 68000 Core Supporting a 16- or 8-Bit M68000 Family-System
• SIB Including:
   Independent Direct Memory Access (IDMA) Controller.
   Interrupt Controller with Two Modes of Operation
   Parallel Input/Output (I/O) Ports, some with Interrupt Capability
   Parallel Input/Output (I/O) Ports on D15-D8 in 8 bit mode
   On-Chip 1152-Byte Dual-Port RAM
   Three Timers Including a Watchdog Timer
   New Periodic Interrupt Timer (PIT)
   Four Programmable Chip-Select Lines with Wait-State Generator Logic
   Programmable Address Mapping of the Dual-Port RAM and IMP Registers
   On-Chip Clock Generator with Output Signal
   On-Chip PLL Allows Operation with 32kHz or 4MHz Crystals
   Glueless Interface to EPROM, SRAM, Flash EPROM, and EEPROM
   Allows Boot in 8-bit Mode, and Running Switch to 16-bit Mode
   System Control:
   System Status and Control Logic
   Disable CPU Logic (Slave Mode Operation)
   Hardware Watchdog
   New Low-Power (Standby) Modes With Wake-up From 2 Pins or PIT
   Freeze Control for Debugging (Available Only in the PGA Package)
   DRAM Refresh Controller
• CP Including:
   Main Controller (RISC Processor)
   Two Independent Full-Duplex Serial Communications Controllers (SCCs)
   Supporting Various Protocols:
   High-Level/Synchronous Data Link Control (HDLC/SDLC)
   Universal Asynchronous Receiver Transmitter (UART)
   Binary Synchronous Communication (BISYNC)
   Transparent Modes
   Autobaud Support Instead of DDCMP and V.110
   Boot from SCC Capability
   Four Serial DMA Channels for the Two SCCs
   Flexible Physical Interface Accessible by SCCs Including:
   Motorola Interchip Digital Link (IDL)
   General Circuit Interface (GCI, Also Known as IOM1-2)
   Pulse Code Modulation (PCM) Highway Interface
   Nonmultiplexed Serial Interface (NMSI) Implementing Standard Modem Signals
   SCP for Synchronous Communication
   Two Serial Management Controllers (SMCs) To Support IDL and GCI Auxiliary Channels
• 100 Pin Thin Quad Flat Pack (TQFP) Packaging

The LC302 excels in several applications areas.

First, any application using the 68302, but not needing all three serial channels is a potential candidate for the LC302. Note however, that the LC302 sacrifices most of the provision for external bus mastership, thus the LC302 may not be appropriate where the 68302 is used as part of larger systems.

Second, the LC302 excels in low power and portable applications. The inclusion of a static 68000 core coupled with the low power modes built into the device make it ideal for handheld, or other low power applications. The new 32 kHz or 4 MHz PLL option greatly reduces the total power budget of the designer's board, and allows the LC302 to be an effective device in low power systems. The LC302 can then optionally generate a full frequency clock for use by the rest of the board. During low power modes, the new periodic interrupt timer (PIT) allows the device to be woken up at regular intervals. In addition, two pins allow the device to be woken up from low power modes.

Third, given that the LC302 is packaged in a 100TQFP package, it allows the 68302 to be used in space critical applications, as well as height critical applications such as PCMCIA cards.

Fourth, since the disable CPU mode (also known as slave mode) is still retained, the LC302 can function as a fully intelligent DMA-driven peripheral chip containing serial channels, timers, and chip selects, etc.

The LC302 has some specific differences from the 68302. Most of these differences simply result from the reduction in pins from 132 on the original 68302, to 100 pins on the LC302.

The following features have been removed or modified from the 68302 in order to make the LC302 possible.
• SCC3 and its baud rate generator (BRG3) are removed.
• External masters are not able to take the bus away from the LC302 except through a simple scheme using the HALT pin. This restriction does not apply to using the LC302 in CPU disabled mode (slave mode), in which case BR, BG, and BGACK are all available (they replace the IPL2-0 pins).
• Although the Independent DMA (IDMA) is still available, the external IDMA request pins (DREQ, DACK, and DONE) have been eliminated.
• Four address lines have been eliminated, giving a total of 20 address lines. However,the LC302 supports more than a 1 MB addressing range, since each of the four chip selects still decodes a 24-bit address. This allows a total of 4 MB to be addressed.
• Since the function code pins and AVEC have been removed, interrupt acknowledgment to external devices is only provided on levels one, six, and seven.
• The DDCMP and V.110 protocols have been removed.
• The total list of pins removed is: A23-A20, FC2-FC0†, AVEC^† , RMC, IAC†, BERR, BR,BG, BGACK, BCLR, IACK1, IACK6, IACK7, DREQ, DACK, DONE, BRG1, FRZ^† , TOUT1, NC1, NC3, TCLK3, RTS3, CTS3, CD3, plus 5 power and ground pins.
• The SCP pins are now muxed with PA8, PA9, and PA10. The TXD3, RXD3, and RCLK3 functions associated with SCC3 are eliminated.
• The UDS, LDS, and R/W pins are not available except in slave mode, where they replace the WEH, WEL, and OE pins. Instead, the new pins WEH, WEL, and OE have been defined for glueless interfacing to memory.
• PA12 is now muxed with the MODCLK pin, which is associated with the 32 kHz or 4 MHz PLL. The MODCLK pin is sampled after reset, and then becomes PA12.
• New VCCsyn, GNDsyn, and XFC pins have been added in support of the on-chip PLL.
• For purposes of emulation support only, a special 132 PGA version is supported. This version adds back the FC2-0, IAC, FRZ, and AVEC pins. The FC2-0 pins allow bus cycles to be distinguished between program and data accesses, interrupt cycles, etc. The IAC, FRZ, and AVEC pins are provided so that emulation vendors can quickly retrofit their existing 68302 emulator designs to support the LC302.