MC68L11D0

• Expanded 16-bit timer system with four-stage programmable prescaler
• Non-return-to-zero (NRZ) serial communications interface (SCI)
• Power-saving stop and wait modes
• 64 Kbytes memory addressability
• Multiplexed address/data bus
• Serial peripheral interface (SPI)
• 4 Kbytes of one-time programmable read-only memory (OTPROM)
• 8-bit pulse accumulator circuit
• 192 bytes of static random-access memory (RAM) (all saved during standby)
• Real-time interrupt (RTI) circuit
• Computer operating properly (COP) watchdog system
• Available in these packages:
   40-pin plastic dual in-line package (DIP)
   44-pin plastic leaded chip carrier (PLCC)
   44-pin plastic quad flat pack (QFP)

The central element in the SPI MC68L11D0 system is the block containing the shift register and the read data buffer. MC68L11D0 is single buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter until the previous transfer is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. As long as the first character of MC68L11D0 is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition occurs. A single MCU register address is used for reading data from the read data buffer, and for writing data to the shifter.

The SPI status block represents the SPI status functions of MC68L11D0 (transfer complete, write collision, and mode fault) performed by the serial peripheral status register (SPSR). The SPI control block represents those functions that control the SPI system through the serial peripheral control register (SPCR).