MC68HC711PH8

(1) All voltages are with respect to V_SS.
(2) Maximum current drain per pin is for one pin at a time, observing maximum power dissipation limits.

Note: This device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. However, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. For maximum reliability all unused inputs should be tied to either V_SS or V_DD.

The central element of MC68HC711PH8 in the SPI system is the block containing the shift register and the read data buffer (see Figure 7-1). The system is single buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter until the previous transfer of MC68HC711PH8 is complete; however,  eceived data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition occurs. A single MCU register address is used for reading data from the read data buffer and for writing data to the shifter.

The SPI MC68HC711PH8 status block represents the SPI status functions (transfer complete, write collision, and mode fault) performed by the serial peripheral status register (SPSR). The SPI MC68HC711PH8 control block represents those functions that control the SPI system through the serial peripheral control register (SPCR).