MC68HC08BD24

• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and 68HC05 families
• Low-power design; fully static with stop and wait modes
• 5V operating voltage
• 6MHz internal bus frequency, with 24MHz external crystal
• 24,576 + 512 bytes of on-chip read-only memory (ROM)
• 512 bytes of on-chip random access memory (RAM)
• Sync signal processor with the following features:
   Horizontal and vertical frequency counters
   Low vertical frequency indicator (40.7Hz)
   Polarity controlled Hsync and Vsync outputs from separate ync or composite sync inputs
   Internal generated free-running Hsync and Vsync pulses
   CLAMP pulse output to the external pre-amp chip
• 6-channel, 8-bit analog-to-digital converter (ADC)
• 16-channel, 8-bit pulse width modulator (PWM)
• DDC12AB¹ odule with the following:
  DDC1 hardware
  Multi-master IIC hardware for DDC²AB; with dual address
• 16-bit, 2-channel timer interface module (TIM) with selectable nput capture, output compare, and PWM capability on one hannel
• 32 general purpose input/output (I/O) pins, including:
   32 shared-function I/O pins
  4 open-drain I/O pins
• System protection features:
  Optional computer operating properly (COP) reset
  Illegal opcode detection with reset
  Illegal address detection with reset
• ROM security1
• Master reset pin with internal pull-up and power-on
• IRQ with programmable pull-up and schmitt-trigger
• 42-pin SDIP and 44-pin QFP packages

• Enhanced HC05 Programming Model
• Extensive Loop Control Functions
• 16 Addressing Modes (Eight More Than the HC05)
• 16-Bit Index Register and Stack Pointer
• Memory-to-Memory Data Transfers
• Fast 8 ´ 8 Multiply Instruction
• Fast 16/8 Divide Instruction
• Binary-Coded Decimal (BCD) Instructions
• Optimization for Controller Applications
• Third Party C Language Support

 

NOTE:
1. Voltages referenced to V_SS.

NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric ields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum- ated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range V_SS £ (V_IN or V_OUT) V_DD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either V_SS or V_DD.)