DescriptionThe low-cost MC68HC05K3 microcontroller (MCU) is a member of the M68HC05 Family of microprocessors. MC68HC05K3 has 64 bytes of user RAM, 128 bits of personality electronically erasable programmable ROM (PEEPROM), and 928 bytes of user ROM.This device is available in the 16-pin plastic dual in-line package (PDIP),16-pin small outline integrated circuit (SOIC) package, and 20-pin super small outline (SSOP) package.
The MC68HC05K3 has the following features include:(1)low-cost HC05 core; (2)16-pin PDIP, 16-pin SOIC package, or 20-pin SSOP; (3)928 bytes of user ROM, including eight bytes of user vectors; (4)64 bytes of user RAM; (5)low-power operation at 1.8 V ?VDD minimum (EEPROM read only); (6)128 bits of personality EEPROM (not memory mapped) programmed using CPU software or with on-chip serial programming ROM; (7)on-chip charge pump for in-circuit programming of the personality EEPROM at 2.7 to 5.5 Vdc; (8)8-bit free-running timer; (9)4-stage selectable real-time interrupt generator.
The absolute maximum ratings of the MC68HC05K3 are:(1)current drain per pin excluding Vdd and Vss:25W;(2)storage temperature range: -65 to +150°C;(3)supply voltage:-0.3 to +7.0V;(4)input voltage:Vss-0.3 to Vdd + -0.3V.Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed.Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
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MC68HC05K3 Data Sheet
