MC68360FE25V

• CPU32+ Processor (4.5 MIPS at 25 MHz)
  -32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)
  -Background Debug Mode
  -Byte-Misaligned Addressing

• Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
• Up to 32 Address Lines (At Least 28 Always Available)
• Complete Static Design (025-MHz Operation)

• Slave Mode To Disable CPU32+ (Allows Use with External Processors)
  -Multiple QUICCs Can Share One System Bus (One Master)
  -MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion Chip and Intelligent Peripheral
    (22 MIPS at 25 MHz)
  -Also Supports External MC68030-Type Bus Masters
  -All QUICC Features Usable in Slave Mode
• Memory Controller (Eight Banks)

  -Contains Complete Dynamic Random-Access Memory (DRAM) Controller
  -Each Bank Can Be a Chip Select or Support a DRAM Bank
  -Up to 15 Wait States
  -Glueless Interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random- Access Memory 
    (SRAM), Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc.
  -Four CAS lines, Four WE lines, One OE line
  -Boot Chip Select Available at Reset (Options for 8-, 16-, or 32-Bit Memory)
  -Special Features for MC68040 Including Burst Mode Support

• Four General-Purpose Timers
  -Superset of MC68302 Timers
  -Four 16-Bit Timers or Two 32-Bit Timers
  -Gate Mode Can Enable/Disable Counting

• Two Independent DMAs (IDMAs)
  -Single Address Mode for Fastest Transfers
  -Buffer Chaining and Auto Buffer Modes
  -Automatically Performs Efficient Packing
  -32-Bit Internal and External Transfers

• System Integration Module (SIM60)
  -Bus Monitor
  -Double Bus Fault Monitor
  -Spurious Interrupt Monitor
  -Software Watchdog
  -Periodic Interrupt Timer
  -Low Power Stop Mode
  -Clock Synthesizer
  -Breakpoint Logic Provides On-Chip Hardware Breakpoints
  -External Masters May Use On-Chip Features Such As Chip Selects
  -On-Chip Bus Arbitration with No Overhead for Internal Masters
  -IJTAG Test Access Port

• Interrupts
  -Seven External IRQ Lines
  -12 Port Pins with Interrupt Capability
  -16 Internal Interrupt Sources
  -Programmable Priority Between SCCs
  -Programmable Highest Priority Request

• Communications Processor Module (CPM)
  -RISC Controller
  -Many New Commands (e.g., Graceful Stop Transmit, Close RxBD)
  -224 Buffer Descriptors
  -Supports Continuous Mode Transmission and Reception on All Serial Channels
  -2.5 Kbytes of Dual-Port RAM
  -14 Serial DMA (SDMA) Channels
  -Three Parallel I/O Registers with Open-Drain Capability
  -Each Serial Channel Can Have Its Own Pins (NMSI Mode)

• Four Baud Rate Generators
  -Independent (Can Be Connected to Any SCC or SMC)
  -Allows Changes During Operation
  -Autobaud Support Option

• Four SCCs
  -Ethernet/IEEE 802.3 Optional on SCC1 (Full 10-Mbps Support)
  -HDLC/SDLC¹ (All Four Channels Supported at 2 Mbps)
  -HDLC Bus (Implements an HDLC-Based Local Area Network (LAN))
  -AppleTalk²
  -Signaling System #7
  -Universal Asynchronous Receiver Transmitter (UART)
  -Synchronous UART
  -Binary Synchronous Communication (BISYNC)
  -Totally Transparent (Bit Streams)
  -Totally Transparent (Frame Based with Optional Cyclic Redundancy Check (CRC))
  -Profibus (RAM Microcode Option)
  -Asynchronous HDLC
  (RAM Microcode Option)
  -DCMP³ (RAM Microcode Option)
  -V.14 (RAM Microcode Option)
  -X.21 (RAM Microcode Option)

• Two SMCs
  -UART
  -Transparent
  -General Circuit Interface (GCI) Controller
  -Can Be Connected to the Time-Division Multiplexed (TDM) Channels

• One SPI
  -Superset of the MC68302 SCP
  -Supports Master and Slave Modes
  -Supports Multimaster Operation on the Same Bus
• Time-Slot Assigner

• Supports Two TDM Channels
  -Each TDM Channel Can Be T1, CEPT, PCM Highway, ISDN Basic Rate, ISDN Primary Rate, User Defined
  -1- or 8-Bit Resolution
  -Allows Independent Transmit and Receive Routing, Frame Syncs, Clocking
  -Allows Dynamic Changes
  -Can Be internally Connected to Six Serial Channels (Four SCCs and Two SMCs)

• Parallel Interface Port
  -Centronics⁴ Interface Support
  -Supports Fast Connection Between QUICCs

• 240 Pins Defined: 241-Lead Pin Grid Array (PGA) and 240-Lead Plastic Quad Flat Pack (PQFP)

The MC68360 QUad Integrated Communication Controller (QUICC^TM ) is a versatile onechip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. MC68360FE25V particularly excels in communications activities. The QUICC (pronounced "quick") can be described as a next-generation MC68302 with higher performance in all areas of device operation, increased flexibility, major extensions in capability, and higher integration. The term "quad" comes from the fact that there are four serial communications
controllers (SCCs) on MC68360FE25V; however, there are actually seven serial channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).

The purpose of MC68360FE25V is to describe the operation of all QUICC functionality. Although this document has an overview of the CPU32+, the M68000PM/AD M68000 Family Programmer's Reference Manualshould be used in addition to this document. The CPU32RM/AD, M68300 Family CPU32 Reference Manual,, also provides information on the CPU32.