Features: • Object Code Compatible with the MC68020 and Earlier M68000 Microprocessors
• Complete 32-Bit Nonmultiplexed Address and Data Buses
• 16 32-Bit General-Purpose Data and Address Registers
• Two 32-Bit Supervisor Stack Pointers and 10 Special-Purpose Control Registers
• 256-Byte Instruction Cache and 256-Byte Data Cache Can Be Accessed Simultaneously
• Paged MMU that Translates Addresses in Parallel with Instruction Execution and Internal Cache Accesses
• Two Transparent Segments Allow Untranslated Access to Physical Memory To Be D fined for Systems That
Transfer Large Blocks of Data between Predefined Physical Addresses
- e.g., Graphics Applications
• Pipelined Architecture with Increased Parallelism Allows Accesses to Internal Caches To Occur in Parallel
with Bus Transfers and Instruction Execution To Be Overlapped
• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum), Synchronous Bus
Cycles (two clocks minimum), and Burst Data Transfers (one clock minimum) all to the Physical Address Space
• Dynamic Bus Sizing Supports 8-, 16-, 32-Bit Memories and Peripherals
• Support for Coprocessors with the M68000 Coprocessor Interface - e.g., Full IEEE Floating-Point
Support Provided by the MC68881/MC68882 Floating-Point Coprocessors
• 4-Gbyte Logical and Physical Addressing Range
• Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High- Density NMOS)
Gates to be Combined for Maximum Speed, Low Power, and Optimum Die Size
• Processor Speeds Beyond 20 MHz Both improved performance and increased functionality result from the on-chip
implementation of the MMU and the data and instruction caches. The enhanced bus controller and the internal parallelism also provide increased system performance. Finally,
the improved bus interface, the reduction in physical size, and the lower power consumption
combine to reduce system costs and satisfy cost/performance goals of the system designer.ApplicationThis section provides guidelines for using the MC68030. First, it discusses the requirements for adapting the MC68030 to MC68020 designs. Then, it describes the use of the MC68881 and MC68882 coprocessors with the MC68030. The byte select logic is described next, followed by memory interface information. A description of external caches, the use of the STATUS and REFILL signals, and power and ground considerations complete the section.
Specifications
|
Rating |
Symbol |
Value |
Unit |
| Supply Voltage |
VCC |
0.3 to +7.0 |
V |
| Input Voltage |
Vin |
0.5 to +7.0 |
V |
| Operating Temperature Range |
TA |
0 to 70 |
|
| Storage Temperature Range |
Tstg |
55 to 150 |
|
*A continuous clock must be supplied to the MC68030 when it is powered up.DescriptionThe MC68030 is a second-generation full 32-bit enhanced microprocessor from Motorola. The MC68030 is a member of the M68000 Family of devices that combines a central processing unit (CPU) core, a data cache, an instruction cache, an enhanced bus controller, and a memory management unit (MMU) in a single VLSI device. The processor is designed to operate at clock speeds beyond 20 MHz. The MC68030 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.
The MC68030 is upward object code compatible with the earlier members of the M68000 Family and has the added features of an on-chip MMU, a data cache, and an improved bus interface. It retains the flexible coprocessor interface pioneered in the MC68020 and provides full IEEE floating-point support through this interface with the MC68881 or MC68882 floating-point coprocessor. Also, the internal functional blocks of this microprocessor are designed to operate in parallel, allowing instruction execution to be overlapped. In addition to instruction execution, the internal caches, the on-chip MMU, and the external bus controller all operate in parallel.
The MC68030 fully supports the nonmultiplexed bus structure of the MC68020, with 32 bits of address and 32 bits of data. The MC68030 bus has an enhanced controller that supports both asynchronous and synchronous bus cycles and burst data transfers. It also supports the MC68020 dynamic bus sizing mechanism that automatically determines device port sizes on a cycle-by-cycle basis as the processor transfers operands to or from external devices.
A block diagram of the MC68030 is shown in Figure 1-1. The instructions and data required by the processor are supplied from the internal caches whenever possible. The MMU translates the logical address generated by the processor into a physical address utilizing its address translation cache (ATC). The bus controller manages the transfer of data between the CPU and memory or devices at the physical address.
MC68030 Data Sheet
