MC62HC589A

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates

The MC54/74HC589A is similar in function to the HC597, which is not a 3state device. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs.

MC62HC589A consists of an 8bit storage latch which feeds parallel data to an 8bit shift register. Data can also be loaded serially (see Function Table). The shift register output, QH, is a threestate output, allowing this device to be used in busoriented systems.

The HC589A directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs.