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MC5HC390A

Features: • Output Drive Capability: 10 LSTTL Loads• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2 to 6 V• Low Input Current: 1 mA• High Noise Immunity Characteristic of CMOS Devices• In Compliance with the Requirements Defined by...

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MC5HC390A: Features: • Output Drive Capability: 10 LSTTL Loads• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2 to 6 V• Low Input Current: 1 mA• High...

MC5HC390A Data Sheet

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MC5HC390A
Supply Ability:
5000

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Product Details

Description



Features:

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No 7A
• Chip Complexity: 244 FETs or 61 Equivalent Ga


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
vcc DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) 0.5 to VCC + 0.5 V
VOUT DC Output Voltage (Referenced to GND) 0.5 to VCC + 0.5 V
LIN DC Input Current, per Pin ±20 mA
IOUT DC Onput Current, per Pin ±35 mA
ICC DC Supply Current Per Supply Pin ±75 mA
PD Power dissipation in still air piastic DIP
SOIC package
750
500
450		 mW
TSTG Storage Temperature 65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)		 260
300		 °C

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
?Derating - Plastic DIP: 10 mW/ from 65to 125
Ceramic DIP: 10 mW/ from 100 to 125
SOIC Package: 7 mW/ from 65 to 125
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).


Description

The MC54/74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.


MC5HC390A consists of two independent 4bit counters, each composed of a dividebytwo and a dividebyfive section. The dividebytwo and dividebyfive counters have separate clock inputs, and can be cascaded to implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.

Flipflops internal to the counters are triggered by hightolow transitions of the clock input. A separate, asynchronous reset of MC5HC390A is provided for each 4bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals of MC5HC390A are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390A.




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