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MC54HC533A

Features: • Output Drive Capability: 15 LSTTL Loads• Outputs Directly Interface to CMOS, NMOS and TTL• Operating Voltage Range: 2.0 to 6.0 V• Low Input Current: 1.0 mA• High Noise Immunity Characteristic of CMOS Devices• In Compliance with the Requirements Defin...

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MC54HC533A: Features: • Output Drive Capability: 15 LSTTL Loads• Outputs Directly Interface to CMOS, NMOS and TTL• Operating Voltage Range: 2.0 to 6.0 V• Low Input Current: 1.0 mA•...

MC54HC533A Data Sheet

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MC54HC533A
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Product Details

Description



Features:

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 256 FETs or 64 Equivalent Gates


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
vcc DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) 0.5 to VCC + 0.5 V
VOUT DC Output Voltage (Referenced to GND) 0.5 to VCC + 0.5 V
LIN DC Input Current, per Pin ±20 mA
IOUT DC Onput Current, per Pin ±35 mA
ICC DC Supply Current Per Supply Pin ±75 mA
PD Power dissipation in still air piastic DIP
SOIC package
750
500
 mW
TSTG Storage Temperature 65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)		 260
 °C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating - Plastic DIP: 10 mW/C from 65 to 125C
Ceramic DIP: 10 mW/C from 100 to 125C
SOIC Package: 7 mW/C from 65 to 125C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).


Description

The MC54/74HC533A is identical in pinout to the LS533. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

MC54/74HC533A latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The Data appears at the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The Output Enable input of MC54/74HC533A does not affect the state of the latches, but when Output Enable is high, MC54/74HC533A outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled. The HC533A is identical in function to the HC563 but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.

MC54/74HC533A are similar in function to the HC373A, which has noninverting outputs.




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