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MC54HC260A

Features: • Output Drive Capability: 10 LSTTL Loads• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2 to 6 V• Low Input Current: 1 µA• High Noise Immunity Characteristic of CMOS Devices• In Compliance with the Requirements Defi...

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MC54HC260A: Features: • Output Drive Capability: 10 LSTTL Loads• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2 to 6 V• Low Input Current: 1 µA•...

MC54HC260A Data Sheet

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Part Number:
MC54HC260A
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 202 FETs or 50.5 Equivalent Gates


Specifications

Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD

Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
SSOP Package†
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
TL
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP,
SOIC or TSSOP Package
(Ceramic DIP)
260
300
C



Description

The MC54/74HC259A is identical in pinout to the LS259. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC259A has four modes of operation as shown in the mode selection table. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all nonaddressed latches remaining in their previous states. In the memory mode, all latches of MC54/74HC259A remain in their previous state and are unaffected by the Data or Address inputs. In the oneofeight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode all outputs are LOW and unaffected by the address and data inputs. When operat ing the HC259A as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, MC54/74HC259A should only be done while in the memory mode.




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