MC14094B

Application* ThreeState Outputs* Capable of Driving Two LowPower TTL Loads or One LowPower Schottky TTL Load Over the Rated Temperature Range* Input Diode Protection* Data Latch* Dual Outputs for Data Out on Both Positive and Negative Clock Transitions* Useful for SerialtoParallel Data Conversion*...

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MC14094B Picture
SeekIC No. : 004415302 Detail

MC14094B: Application* ThreeState Outputs* Capable of Driving Two LowPower TTL Loads or One LowPower Schottky TTL Load Over the Rated Temperature Range* Input Diode Protection* Data Latch* Dual Outputs for Da...

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Part Number:
MC14094B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Application

* ThreeState Outputs
* Capable of Driving Two LowPower TTL Loads or One LowPower Schottky TTL Load Over the Rated Temperature Range
* Input Diode Protection
* Data Latch
* Dual Outputs for Data Out on Both Positive and Negative Clock Transitions
* Useful for SerialtoParallel Data Conversion
* PinforPin Compatible with CD4094B



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VDD DC Supply Voltage Range 0.5 to +18.0 V
Vin,Vout
Input or Output Voltage Range(DC or Transient) 0.5 to VDD + 0.5
V
Iin,Iout
Input or Output Current(DC or Transient)per Pin ±10 mA
PD Power Dissipation, per Package (Note 3.) 500 mW
TA Ambient Temperature Range 55 to +125
Tstg Storage Temperature Range 65 to +150
TL Lead Temperature(8Second Soldering) 260



Description

The MC14094B combines an 8stage shift register with a data latch for each stage and a threestate output from each latch.


Data of MC14094B is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QS output data is for use in highspeed cascaded systems. The QS output data of MC14094B is shifted on the following negative clock transition for use in lowspeed cascaded systems.


Data of MC14094B from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high.


Outputs of the eight data latches are controlled by threestate buffers which are placed in the highimpedance state by a logic Low on Output Enable.


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