MC10SX1401

Application• SONET/SDHbased transmission systems, modules, test equipment• ATM using SONET• Add drop multiplexers• Other (nonSONET) data rate transmission systemsPinoutSpecifications Symbol Parameter Value Unit VCC, VCCO,VCCT, AVCC Power Supply (VEE, VEET, AVEE,...

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MC10SX1401 Picture
SeekIC No. : 004415126 Detail

MC10SX1401: Application• SONET/SDHbased transmission systems, modules, test equipment• ATM using SONET• Add drop multiplexers• Other (nonSONET) data rate transmission systemsPinoutSpecif...

floor Price/Ceiling Price

Part Number:
MC10SX1401
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Application

• SONET/SDHbased transmission systems, modules, test equipment
• ATM using SONET
• Add drop multiplexers
• Other (nonSONET) data rate transmission systems



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC, VCCO,
VCCT, AVCC
Power Supply (VEE, VEET, AVEE, GVEE = 0V) 0.5 to +6.5 V
VIN Input Voltage (VEE, VEET, AVEE, GVEE = 0V) 0.5 to +6.5 V
IOUT PECL Output Current Continuous
Surge
50
100
mA
IOUTTTL TTL Output Current 5 mA
TSTG Storage Temperature 50 to +175

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.




Description

The MC10SX1401 receiver (Rx) chip is an integrated deserialization SONET OC3 (155.52 Mb/s) and OC12 (622.08 Mb/s) interface device.

MC10SX1401 performs the data and clock recovery and serialtoparallel conversion functions in conformance with SONET/SDH transmission standards.

High performance and low power of MC10SX1401 is achieved with MOSAIC VE, Motorola's most advanced highperformance silicon Bipolar process. A companion serialization (Tx) chip, the SX1405, is also available.
• Recovers a 155.52/622.08 MHz internal clock from an OC3/OC12 data stream
• Samples, quantizes and demultiplexes the input signal into a parallel TTL data stream
• Generates an EVEN parity bit with the demultiplexed data
• Provides a 155.52 MHz differential PECL timing reference clock
• No external input reference clock is required
• Detects the peak amplitude of the Rx signal and generates a proportional DC voltage
• Provides PLL Frequency Control Monitor and OutofLock Indicator
• Selectable eight or four bit parallel interface
• Single supply operation (+5V)




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