MC10H640

The MC10H/100H640 generates the necessary clocks for the 68030, 68040 and similar microprocessors. MC10H/100H640 is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of parttopart skew, withinpart skew and also duty cycle skew.

The user has a choice of using either TTL or PECL (ECL referenced to +5.0V) for the input clock. TTL clocks of MC10H/100H640 are typically used in present MPU systems. However, as clock speeds increase to 50MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The MC10H/100H640 also uses differential PECL internally to achieve its superior skew characteristic.

The MC10H/100H640 includes dividebytwo and dividebyfour stages, both to achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50MHz processor application would use an input clock running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz (see Logic Symbol).

The MC10H/100H640 version is compatible with MECL 10H^TM ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0V).
• Generates Clocks for 68030/040
• Meets 030/040 Skew Requirements
• TTL or PECL Input Clock
• Extra TTL and PECL Power/Ground Pins
• Asynchronous Reset
• Single +5.0V Supply