Features: • 330 ps Typical Propagation Delay• Maximum Frequency > 4 GHz Typical• PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V• NECL Mode: VCC = 0 V with VEE = −3.0 V to −5.5 V• Open Input Default State• Safety Clamp on Inputs• Q Output Will D...
MC10EP52: Features: • 330 ps Typical Propagation Delay• Maximum Frequency > 4 GHz Typical• PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V• NECL Mode: VCC = 0 V with VEE = −3.0 V ...
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Counter Shift Registers 5V ECL 8-Bit Binary Up Synchronous
Symbol |
Parameter |
Condition1 | Condition2 | Rating |
Unit |
VCC |
PECL Mode Power Supply | VEE = 0 V | 6 |
V |
|
VEE |
NECL Mode Power Supply | VCC=0 V | -6 |
V |
|
VI |
PECL Mode Input Voltage NECL Mode Input Voltage |
VEE = 0 V VCC=0 V |
VI VCC VI VEE |
-6 6 |
V V |
Iout |
Output Current | Continuous Surge |
50 100 |
mA mA |
|
IBB |
VBB Sink/Source | ±0.5 |
|||
TA |
Operating Temperature Range | 40 to +85 |
|||
Tstg |
Storage Temperature Range | 65 to +150 |
|||
JA |
Thermal Resistance (Junction to Ambient) | 0 LFPM 500 LFPM |
SOIC−8 SOIC−8 |
190 130 |
/W /W
|
JC |
Thermal Resistance (Junction to Case) | std bd | SOIC−8 |
41 to 44 |
/W |
JA |
Thermal Resistance (Junction to Ambient) | 0 LFPM 500 LFPM |
TSSOP−8 TSSOP−8 |
185 140 |
/W
/W |
JC |
Thermal Resistance (Junction to Case) | std bd | TSSOP−8 |
41 to 44 |
/W |
Tsol |
Wave Solder | <2 to 3 sec @ 248°C | 265 |
The MC10EP/100EP52 is a differential data, differential clock Dflip−flop. The device is pin and functionally equivalent to the EL52 device.
Data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the MC10EP/100EP52 to also be used as a negative edge triggered device.
The EP52 employs input clamping circuitry of MC10EP/100EP52 so that under open input conditions (pulled down to VEE) the outputs of the device will remain stable.
The 100 Series contains temperature compensation.