Features: •450 ps Typical Propagation Delay•Maximum Frequency > 3.0 GHz Typical•Asynchronous Master Reset•20 ps Skew Within Device, 35 ps Skew Device−To−Device•PECL Mode Operating Range: VCC= 3.0 V to 5.5 VWith VEE=0 V•NECL Mode Operating Range: V...
MC10EP451MC100EP451: Features: •450 ps Typical Propagation Delay•Maximum Frequency > 3.0 GHz Typical•Asynchronous Master Reset•20 ps Skew Within Device, 35 ps Skew Device−To−Device...
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Counter Shift Registers 5V ECL 8-Bit Binary Up Synchronous
Symbol |
Parameter |
Condition 1 |
Condition 2 |
Rating |
Unit |
VCC |
PECL Mode Power Supply |
VEE= 0 V |
6 |
V | |
VEE |
NECL Mode Power Supply |
VCC= 0 V |
−6 |
V | |
VI | PECL Mode Input Voltage NECL Mode Input Voltage |
VEE= 0 V VCC= 0 V |
VIVCC VIVEE |
6 −6 |
V V |
IOUT | Output Current | Continuous Surge |
50 100 |
mA mA | |
TA | Operating Temperature Range | −40 to +85 | |||
Tsty | Storage Temperature Range | −65 to +150 | |||
JA | Thermal Resistance (Junction to Ambient) | 0 lfpm 500 lfpm |
LQFP−32 LQFP−32 |
80 55 |
/W /W |
JC | Thermal Resistance (Junction to Case) | Standard Board |
LQFP−32 |
12 to 17 | /W |
Tsol | Wave Solder | <2 to 3 sec @ 248°C | 265 |
The MC10/100EP451 is a 6−bit fully differential register withcommon clock and single−ended Master Reset (MR). It is ideal forvery high frequency applications where a registered data path isnecessary.
All inputs of MC10/100EP451 have a 75 k pulldown resistor internally. Differentialinputs have an override clamp. Unused differential register inputs canbe left open and will default LOW. When the differential inputs areforced to < VEE + 1.2 V, the clamp will override and force the output toa default state. When in the default state, and since the flip−flop is edgetriggered, the output reaches a determined, but not predicted, validstate.
The positive transition of CLK (pin 4) will latch the registers.Master Reset (MR) HIGH will asynchronously reset all registersforcing Q outputs to go LOW.
The 100 Series contains temperature compensation.