MC10EP195

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition.

The delay section MC10/100EP195 consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D[10:0]. The approximate delay values of MC10/100EP195 for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 3.

Because the MC10/100EP195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for controlling Pins 14 and 15, CASCADE and CASCADE, also latched by LEN, in cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Switching devices from all "1" states on D[0:9] with SETMAX LOW to all "0" states on D[0:9] with SETMAX HIGH will increase the delay equivalent to "D0", the minimum increment. Select input pins D[10:0] may be threshold controlled of MC10/100EP195 by combinations of interconnects between VEF(pin 7) and VCF(pin 8) for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input levels, leave VCFand VEFopen. For ECL operation, short VCF andVEF(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply reference to VCFand leave open VEFpin. The 1.5 V reference voltage to VCFpin can be accomplished by placing a 2.2