DescriptionThe MC10E193FN is designed as an error detection and correction (EDAC) circuit. Modified hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also provided at the PGEN...
MC10E193FN: DescriptionThe MC10E193FN is designed as an error detection and correction (EDAC) circuit. Modified hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic sy...
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Counter Shift Registers 5V ECL 8-Bit Binary Up Synchronous
The MC10E193FN is designed as an error detection and correction (EDAC) circuit. Modified hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also provided at the PGEN pin, after odd/even parity control and gating with the BPAR input. This output of MC10E193FN also feeds to a 1-bit shiftable register, for use as part of a scan ring.
MC10E193FN has six features. (1)Hamming code generation. (2)8-bit word, expandable. (3)Provides parity of whole word. (4)Scannable parity register. (5)Extended 100E Vee range of -4.2V to -5.46V. (6)75kW input pulldown resistors. Those are all the main features.
Some DC electrical characteristics of MC10E193FN have been concluded into several points as follow. (1)Its input high current would be max 150uA. (2)Its power supply current would be typ 112mA and max 134mA. And so on. Those are all the main DC electrical characteristics.
Also some AC electrical characteristics of MC10E193FN are concluded as follow. (1)Its propagation delay to output B to P1, P2, P3, P4 would be min 350ps and typ 700ps and max 1000ps. (2)Its propagation delay to output B to P5 would be min 400ps and typ 775ps and max 1150ps. (3)Its propagation delay to output EV/OD, BPAR to PGEN would be min 350ps and typ 650ps and max 850ps. (4)Its propagation delay to output B to PGEN would be min 600ps and typ 1000ps and max 1450ps. (5)Its propagation delay to output CLK to PARERR would be min 300ps and typ 550ps and max 850ps. (6)Its setup time SHIFT would be min 400ps and typ 150ps. (7)Its setup time S-IN would be min 300ps and typ 50ps. (8)Its setup time HOLD would be min 750ps and typ 350ps. (9)Its setup time EN would be min 500ps and typ 250ps. (10)Its setup time EV/OD would be min 1300ps and typ 850ps. (11)Its setup time BPAR would be min 1300ps and typ 850ps. And so on. If you have any question or suggestion or want to know more information about MC10E193FN please contact us for details. Thank you!