MC10E1651

The timing diagram (Figure 3) is presented to illustrate the MC10E1651's compare and latch features. When the signal on the LEN pin is at a logic high level, the device is operating in the "compare mode," and the signal on the input arrives at the output after a nominal propagation delay (tPHL , tPLH). The input signal must be asserted for a time, t_s , prior to the negative going transition on LEN and held for a time, t_h , after the LEN transition. After time t_h, the latch is operating in the "latch mode," thus transitions on the input do not appear at the output. The device continues to operate in the "latch mode" until the latch is asserted once again. Moreover, the LEN pulse must meet the minimum pulse width (tpw)  requirement to effect the correct input-output relationship. Note that the LENwaveform in Figure 3 shows the LENsignal swinging around a reference labeled VBB ; this INT waveform emphasizes the requirement that LEN follow typical ECL 10KH logic levels because VBB  is the INTinternally generated reference level, hence is nominally at the ECL VBB level.

Finally, V_OD is the input voltage overdrive and represents the voltage level beyond the threshold level (V_THR ) to which  the input is driven. As an example, if the threshold level is set on one of the comparator inputs as 80mV and the input signal swing on the complementary input is from zero to 100mV, the positive going overdrive would be 20mV and the negative going overdrive would be 80mV. The result of differing overdrive levels is that the devices have shorter propagation delays with greater overdrive because the threshold level is crossed sooner than the case of lower overdrive levels. Typically, semiconductor manufactures refer to the threshold voltage as the input offset voltage (VOS) since the threshold voltage is the sum of the externally supplied reference voltage and inherent device offset voltage.

The MC10E1651 is functionally and pin-for-pin compatible with the MC1651 in the MECL III family, but is fabricated using Motorola's advanced MOSAIC III process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in both a 16-pin DIP and a 20-pin surface mount package.

The latch enable (LENa and LENb ) input pins operate from standard ECL 10KH logic levels. When the latch enable is at a logic high level the MC10E1651 acts as a comparator, hence Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When the latch enable input goes to a low logic level, the outputs of MC10E1651 are latched in their present state providing the latch enable setup and hold  timeconstraints are met.