MC100LVEP210

The MC100LVEP210 is a low skew 1to5 dual differential driver, designed with clock distribution in mind. The LVECL/LVPECL input signals can be either differential or singleended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the MC100LVEP210 is operating in LVPECL mode. The LVEP210 specifically guarantees low outputtooutput skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot.

To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50W even if only one side is being used. When fewer than all ten pairs are used, identically terminate all the output pairs on the same package side whether used or unused. If no outputs of MC100LVEP210 on a single side are used, then leave these outputs open (unterminated). MC100LVEP210 will maintain minimum output skew. Failure to do this will result in a 1020ps loss of skew margin (propagation delay) in the output(s) in use.

The MC100LVEP210, as with most other LVECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP210 to be used for high performance clock distribution in +3.3V or +2.5V systems. Single ended input operation is limited to a VCC . 3.0V in PECL mode, or VEE 3 3.0V in ECL mode.

Designers can take advantage of the LVEP210's performance to distribute low skew clocks across the backplane or the board. In a lVPECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information about MC100LVEP210 on using PECL, designers should refer to Application Note AN1406/D.