MC100LVEP111

The MC100LVEP111 is a low skew 1to10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The LVECL/LVPECL input signals can be either differential or singleended (if the VBB output is used). HSTL inputs of MC100LVEP111 can be used when the LVEP111 is operating under LVPECL conditions.

The MC100LVEP111 specifically guarantees low outputtooutput skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot.

To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50
even if only one side is being used. When MC100LVEP111 is fewer than all ten pairs are used, identically terminate all the output pairs on the same package side whether used or unused. If no outputs on a single side are used, then leave these outputs open (unterminated). MC100LVEP111 will maintain minimum output skew. Failure to do this will result in a 1020ps loss of skew margin (propagation delay) in the output(s) in use.

The MC100LVEP111, as with most other LVECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the MC100LVEP111 to be used for high performance clock distribution in +3.3V or +2.5V systems. Single ended input operation is limited to a VCC . 3.0V in LVPECL mode, or VEE 3 3.0V in LVECL mode. Designers can take advantage of the LVEP111's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information about MC100LVEP111 on using LVPECL, designers should refer to Application Note AN1406/D.