MC100LVEL39

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but is specified for operation at the standard 100K ECL voltage supply. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended LVECL or, if positive power supplies are used, LVPECL input signal. In addition, by using the V_BB output, a sinusoidal source can be AC coupled into the MC100LVEL39 (see Interfacing section of the ECLin PSE Data Book DL140/D). If a single-ended input is to be used, the V_BB output should be connected to the CLK input and bypassed to ground via a 0.01mF capacitor. The V_BB output is designed to act as the switching reference for the input of the LVEL39 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current.

The common enable (EN ) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. MC100LVEL39 avoids any chance of generating a runt clock pulse on the internal clock when the MC100LVEL39 is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Upon startup, the internal flip-flops of MC100LVEL39 will attain a random state; therefore, for systems which utilize multiple LVEL39s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one LVEL39, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of a single device.