Clock Buffer 3.3V ECL Dual 1:4
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Counter Shift Registers 5V ECL 8-Bit Binary Up Synchronous
Number of Outputs : | 18 | Max Input Freq : | 700 GHz |
Propagation Delay (Max) : | 0.9 ns | Supply Voltage - Max : | +/- 3.8 V |
Supply Voltage - Min : | +/- 3 V | Maximum Operating Temperature : | + 85 C |
Minimum Operating Temperature : | - 40 C | Package / Case : | PLCC-28 |
Packaging : | Tube |
The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The MC100LVE210 features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a parttopart skew down to an outputtooutput skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111's to accomplish the same task. The MC100LVE210 works from a 3.3V supply while the MC100E210 provides identical function and performance from a standard 4.5V 100E voltage supply.
Technical/Catalog Information | MC100LVE210FN |
Vendor | ON Semiconductor |
Category | Integrated Circuits (ICs) |
Type | Fanout Buffer |
Voltage - Supply | 3 V ~ 3.8 V |
Number of Outputs | 9 |
Input | ECL, PECL |
Output | ECL, PECL |
Frequency-Max | 700GHz |
Package / Case | 28-PLCC |
Packaging | Tube |
Operating Temperature | -40°C ~ 85°C |
Lead Free Status | Contains Lead |
RoHS Status | RoHS Non-Compliant |
Other Names | MC100LVE210FN MC100LVE210FN |