MC100LVE111

Features:

• 200 ps Part-to-Part Skew
• 50 ps Output-to-Output Skew
• ESD Protection: >2 KV HBM, >200 V MM
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V_CC= 3.0 V to 3.8 V with V_EE = 0 V
• NECL Mode Operating Range: V_CC= 0 V with V_EE = 3.0 V to 3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default LOW with Inputs Open or at V_EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL94 code V0 @ 1/8", Oxygen Index 28 to 34
• Transistor Count = 250 devices


Pinout




Specifications

Symbol	Parameter	Condition 1	Condition 2	Rating	Units
VCC	PECL Mode Power Supply	VEE = 0 V		8 to 0	V
VEE	NECL Mode Power Supply	VCC = 0 V		8 to 0	V
VI	PECL Mode Input Voltage NECL Mode Input Voltage	VEE = 0 V VCC = 0 V	VI  VCC VI  VEE	6 to 0 6 to 0	V V
Iout	Output Current	Continuous Surge		50 100	mA mA
IBB	VBB Sink/Source			± 0.5	mA
TA	Operating Temperature Range			40 to +85	°C
Tstg	Storage Temperature Range			65 to +150	°C
JA	Thermal Resistance (Junction to Ambient)	0 LFPM 500 LFPM	28 PLCC 28 PLCC	63.5 43.5	°C/W °C/W
JC	Thermal Resistance (Junction to Case)	std bd	28 PLCC	22 to 26 ± 5%	°C/W
Tsol	Wave Solder	<2 to 3 sec @ 248°C		265	°C

Description

   The MC100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC100LVE111's function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be either differential or single-ended if the V_BB output is used. The signal is fanned out to 9 identical differential outputs.

   The MC100LVE111 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within MC100LVE111, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device.

   To ensure that the tight skew specification is met MC100LVE111 is necessary that both sides of the differential output are terminated into 50 W, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 1020 ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of
skew margin.

   The MC100LVE111, as with most other ECL devices, can be operated from a positive V_CC supply in PECL mode. This allows the MC100LVE111 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the MC100LVE111's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating
GTL, parallel termination offers the lowest power by taking advantage of the 1.2 V supply as a terminating voltage. For more information on using PECL, designers should refer to Application Note AN1406/D.

   The VBB pin, an internally generated voltage supply, is available to MC100LVE111 only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. V_BB may also rebias AC coupled inputs. When used, decouple V_BB and V_CC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V_BB should be left open.