MC100H605

Features:

•Differential ECL Data and Clock Inputs
•24mA Sink, 24mA Source TTL Outputs
•Dual Power Supply
•Multiple Power and Ground Pins to Minimize Noise
•2.0ns ParttoPart Skew


Pinout




Specifications

100H ECL DC CHARACTERISTICS (VCCT= +5.0V ±5%; VEE= 5.20V ±5%)
Symbol	Characteristic	0°C			25°C			85°C			Unit	Condition
		Min	Typ	Max	Min	Typ	Max	Min	Typ	Max
IEE	Supply Current		63	75		63	75		61	75	mA
IIH	Input HIgh Current			225			145			145	µA
IIL	Input Low Current	0.5			0.5			0.5			µA
VIH	Input High Voltage	1165		880	1165		880	1165		880	mV
VIL	Input Low Voltage	1810		1475	1810		1475	1810		1475	mV
VBB	Output Bias Voltage	1400		1280	1400		1280	1400		1200	mV
VDiff	Input Differential Voltage	150			150			150			mV
Vmax CMRR	Input Common Mode Reject Range			0			0			0	mV
Vmin CMRR	Input Common Mode Reject Range	2000 2200 2400			2000 2200 2400			2000 2200 2400			mV	VEE= 4.20 VEE= 4.50 VEE= 4.80

Description

   The MC10/100H605 is a 6bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs MC10/100H605 feature balanced 24mA sink/source capabilities for driving transmission lines. With its differential ECL inputs and TTL outputs the H605 device is ideally suited for the receive function of a HPPI bus type boardtoboard interface application. The on chip registers simplify the task of synchronizing the data between the two boards.A V BB reference voltage of MC10/100H605 is supplied for use with singleended data or clock. For singleended applications the VBB output should be connected to the "bar" inputs (Dn or CLK) andbypassed to ground via a 0.01 µF capacitor.To minimize the skew of the device differential clocks should be used.

   The ECL level Master Reset pin of MC10/100H605 is asynchronous and common to all flipflops. A "HIGH" on the Master Reset forces the Q outputs "LOW".The MC10/100H605 is available in either ECL standard: the 10H device iscompatible with MECL 10H logic levels while the 100H device iscompatible with 100K logic levels.