MC100ES8111

The MC100ES8111 is designed for low skew clock distribution systems and supports clock frequencies up to 625 MHz. The MC100ES8111 accepts two clock sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential HSTL compatible outputs.

In order to meet the tight skew specific ation of the MC100ES8111, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all 10 outputs of MC100ES8111 are used, the output pairs on the same package side as the parts being used on that side should be terminated.

The HSTL compatible output levels are generated with an open emitter architecture. MC100ES8111 minimizes part-to-part and output-to-output skew. The open-emitter outputs require a 50 Ω DC termination to GND (0V). The output supply voltage of MC100ES8111 can be either 1.5V or 1.8V, the core voltage supply is 3.3V. The output enable control is synchronized inte rnally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The MC100ES8111 is packaged in a 7x7 mm² 32-lead LQFP package.