MC100ES7111

The MC100ES7111 is designed for low skew clock distribution systems and supports clock frequencies up to 1000 MHz¹. Thedevice accepts two clock sources. The CLK0 input accepts LVDS or HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal of MC100ES7111 is distributed to 10 identical, differential LVDS compatible outputs.

The output enable control of MC100ES7111 is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The MC100ES7111 is packaged in a7x7 mm_²32-lead LQFP package.