MC100ES6220

The MC100ES6220 is designed for low skew clock distribution systems and supports clock frequencies up to 1 GHz. The device consists of two independent clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output.

In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated.

The MC100ES6220 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the MC100ES6220 supports positive (PECL) and negative (ECL) supplies. The MC100ES6220 is pin and function compatible to the MC100EP220.