MC100ES6039

The MC100ES6039 is a low skew ÷2/4, ÷4/6 clock generation chip designed  explicitly for low skew clock generation applications. The internal dividers are  synchronous to each other, therefore, the common output edges are all precisely  aligned. The device can be driven by either a differential or single-ended ECL or,  if positive power supplies are used, LVPECL input signals. In addition, by using  the VBB output, a sinusoidal source can be AC coupled into the device.

The common enable (EN) is synchronous so that the internal dividers will only  be enabled/disabled when the internal clock is already in the LOW state. This  avoids any chance of generating a runt clock pulse on the internal clock when the  MC100ES6039 is enabled/disabled as can happen with an asynchronous control. The  internal enable flip-flop is clocked on the falling edge of the input clock, therefore,  all associated specification limits are referenced to the negative edge of the clock  input.

Upon startup, the internal flip-flops will attain a random state; therefore, for  systems which utilize multiple MC100ES6039s, the master reset (MR) input must be  asserted to ensure synchronization. For systems which only use one MC100ES6039, the MR pin need not be exercised as the internal divider design ensures  synchronization between the ÷2/4 and the ÷4/6 outputs of a single device. All V_CC  and V_EE pins must be externally connected to power supply to guarantee proper  operation.

The 100ES Series contains temperature compensation.