MC100EP91

Features:

• Maximum Input Clock Frequency > 2.0 GHz Typical
• Maximum Input Data Rate > 2.0 Gb/s Typical
• 500 ps Typical Propagation Delay
• Operating Range: V_CC = 2.375 V to 3.8 V;
   V_EE = −3.0 V to −5.5 V; GND = 0 V
• Q Output will Default LOW with Inputs Open or at GND
• Pb−Free Packages are Available*


Pinout




Specifications

Symbol	Parameter	Condition 1	Condition 2	Rating	Unit
VCC	Positive Power Supply	GND = 0 V		3.8 to 0	V
VEE	Negative Power Supply	GND = 0 V		−6	V
VI	Positive Input Voltage	GND = 0 V	VI VCC	3.8 to 0	V
VOP	Operating Voltage	GND = 0 V	VCC − VEE	9.8	V
Iout	Output Current	Continuous Surge		50 100	mA mA
IBB	PECL VBB Sink/Source			± 0.5	mA
TA	Operating Temperature Range			−40 to +85
Tstg	Storage Temperature Range			−65 to +150
JA	Thermal Resistance (Junction−to−Ambient) JESD 51−3 (1S−Single Layer Test Board)	0 lfpm 500 lfpm	SOIC−20 SOIC−20	90 60	/W /W
JA	Thermal Resistance (Junction−to−Ambient) JESD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias	0 lfpm 500 lfpm	QFN−24 QFN−24	37 32	/W /W
JC	Thermal Resistance (Junction−to−Case)	Standard Board	SOIC−20 QFN−24	30 to 35 11	/W /W
Tsol	Wave Solder                      Pb                                           Pb−Free			225 225

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.


Description

The MC100EP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential NECL output signals (−3.0 V / −5.5 V).

To accomplish the level translation the MC100EP91 requires three power rails. The V_CC pins should be connected to the positive power supply, and the V_EE pin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both V_EE and V_CC should be bypassed to ground via 0.01 F capacitors.

Under open input conditions, the D input will be biased at V_CC/2 and the D input will be pulled to GND. These conditions will force the Q outputs to a low state, and Q outputs to a high state, which will ensure stability.

The V_BB pin, an internally generated voltage supply, is available to this MC100EP91 only. For single-ended input conditions, the unused differential input is connected to V_BB as a switching reference voltage. V_BB may also rebias AC coupled inputs. When used, decouple V_BB and V_CC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.