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MC100EP445FAR2

Serial to Parallel Logic Converters 3.3V/5V ECL 8-Bit

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SeekIC No. : 00448939 Detail

MC100EP445FAR2: Serial to Parallel Logic Converters 3.3V/5V ECL 8-Bit

MC100EP445FAR2 Data Sheet

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Part Number:
MC100EP445FAR2
Mfg:
ON Semiconductor
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Quick Details

Operating Supply Voltage : - 3.3 V, - 5 V, 3.3 V, 5 V Mounting Style : SMD/SMT
Package / Case : LQFP-32 Packaging : Reel    

Description

Packaging : Reel
Mounting Style : SMD/SMT
Operating Supply Voltage : - 3.3 V, - 5 V, 3.3 V, 5 V
Package / Case : LQFP-32


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI  VCC
VI  VEE
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C



Description

The MC100EP445FAR2 is an integrated 8bit differential serial to parallel data converter with asynchronous data synchronization. The device has two modes of operation. CKSEL HIGH mode is designed to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode is designed to operate at twice the internal clock data rate of up to 5.0 Gb/s. The conversion sequence was chosen to convert the first serial bit to Q0, the second bit to Q1, etc.

Two selectable differential serial inputs, which are selected by SINSEL, provide this device with loop-back testing capability. The MC100EP445FAR2 has a SYNC pin which, when held high for at least two consecutive clock cycles, will swallow one bit of data shifting the start of the conversion data from Dn to Dn+1. Each additional shift requires an additional pulse to be applied to the SYNC pin. Control pins are provided to reset and disable internal clock circuitry. Additionally, VBB pin is provided for single-ended input condition. The 100 Series contains temperature compensation.




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