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MC100EP210S

Features: • 20 ps Typical OutputtoOutput Skew• 85 ps Typical DevicetoDevice Skew• 550 ps Typical Propagation Delay• The 100 Series Contains Temperature Compensation• Maximum Frequency > 1 GHz Typical• Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V&#...

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MC100EP210S: Features: • 20 ps Typical OutputtoOutput Skew• 85 ps Typical DevicetoDevice Skew• 550 ps Typical Propagation Delay• The 100 Series Contains Temperature Compensation• Ma...

MC100EP210S Data Sheet

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Part Number:
MC100EP210S
Supply Ability:
5000

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  • 1~5000
  • Unit Price
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 20 ps Typical OutputtoOutput Skew
• 85 ps Typical DevicetoDevice Skew
• 550 ps Typical Propagation Delay
• The 100 Series Contains Temperature Compensation
• Maximum Frequency > 1 GHz Typical
• Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V
• Internal 50   Input Termination Resistors
• LVDS Input/Output Compatible


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Condition1
Condition 2
Rating
Units
VCC
 Power Supply
VEE = 0 V
6
V
VEE
 Power Supply (GND)
VCC = 2.5 V
6
V
VI
 LVDS, LVPECL Input Voltage
VEE = 0 V
VI VCC
6
V
Iout Output Current
Continuous
Surge
50
100
mA
mA

TA
 Operating Temperature Range
40 to +85
Tstg Storage Temperature Range
65 to +150
JA Thermal Resistance (JunctiontoAmbient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
/W
/W
JC Thermal Resistance (JunctiontoCase)
std bd
32 LQFP
12 to 17
/W
Tsol
 Wave Solder
< 2 to 3 sec @ 248°C
265
2. Maximum Ratings are those values beyond which device damage may occur.


Description

The MC100EP210S is a low skew 1to5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs.

The MC100EP210S specifically guarantees low outputtooutput skew. Optimal design, layout, and processing minimize skew within a device and from device to device.

Two internal 50  resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the VTT (VCC2.0 V) supply.

Designers can take advantage of the MC100EP210S performance to distribute low skew LVDS clocks across the backplane or the board. Special considerations are required for differential inputs under No Signal conditions to prevent instability.




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