MC100EP16VC

Features:

· 310 ps Typical Prop Delay Q 380 ps Typical Prop Delay QHG, QHG
· Gain > 200
· Maximum Frequency > 3 GHz Typical
· PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V with V_EE = 0 V
· NECL Mode Operating Range: V_CC = 0 V with V_EE = -3.0 V to -5.5 V
· Open Input Default State
· QHG Output Will Default LOW with D Inputs Open or at V_EE
·V_BB Output


Pinout




Specifications

Symbol	Parameter	Condition 1	Condition 2	Rating	Units
VCC	PECL Mode Power Supply	VEE = 0 V		6	V
VEE	NECL Mode Power Supply	VCC = 0 V		-6	V
VI	PECL Mode Input Voltage NECL Mode Input Voltage	VEE = 0 V VCC = 0 V	VI VCC VI VEE		V V
Iout	Output Current	Continuous Surge		50 100	mA mA
IBB	VBB Sink/Source			± 1.5	mA
TA	Operating Temperature Range			−40 to +85
Tstg	Storage Temperature Range			−65 to +150
JA	Thermal Resistance (Junction−to−Ambient)	0 LFPM 500 LFPM	8 SOIC 8 SOIC	190 130	/W /W
JC	Thermal Resistance (Junction−to−Case)	std bd	8 SOIC	41 to 44	/W
JA	Thermal Resistance (Junction−to−Ambient)	0 LFPM 500 LFPM	8 TSSOP 8 TSSOP	185 140	/W /W
JC	Thermal Resistance (Junction−to−Case)	std bd	8 TSSOP	41 to 44	/W
Tsol	Wave Solder	<2 to 3 sec @ 248°C		265

2. Maximum Ratings are those values beyond which device damage may occur.


Description

The MC100EP16VC is a differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain and enable output.

The MC100EP16VC provides an EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and QHG outputs.

When the EN signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and EN goes HIGH, it will force the Q_HG LOW and the QHG HIGH on the next negative transition of the data input. If the data input is LOW when the EN goes HIGH, the next data transition to a HIGH is ignored and Q_HG remains LOW and QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The Q_HG and QHG outputs remain in their disabled state as long as the EN input is held HIGH. The EN input has no influence on the Q output and the data input is passed on (inverted) to this output whether EN is HIGH or LOW. This MC100EP16VC configuration is ideal for crystal oscillator applications where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output.

The V_BB/D pin is internally dedicated and available for differential interconnect. V_BB/D may rebias AC coupled inputs. When used, decouple V_BB/D and V_CC via a 0.01 F capacitor and limit current sourcing or sinking to 1.5 mA. When not used, V_BB/D should be left open.

The 100 Series contains temperature compensation.