MC100EP14

• 400 ps Typical Propagation Delay
• 100 ps Device−to−Device Skew
• 25 ps Within Device Skew
• Maximum Frequency > 2 GHz Typical
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode: V_CC = 3.0 V to 5.5 V with V_EE = 0 V
• NECL Mode: V_CC = 0 V with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• These are Pb−Free Devices

The MC100EP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single−ended (if the V_BB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.

The MC100EP14 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.

To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.
The common enable (EN ) is synchronous, outputs are enabled/ disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.

The MC100EP14, as with most other ECL devices, can be operated from a positive V_CC supply in PECL mode. This allows the EP14 to be used for high performance clock distribution in 5.0 V systems. Designers can take advantage of the EP14's performance to distribute low skew clocks across the backplane or the board.