MC100EL15D

The MC100EL15D is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the V  output should be connected to theCLK input V_BBand bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single-ended input conditions, as a result this pin can only source/sink up
to 0.5mA of current.
The MC100EL15D features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN ) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.