MC100E160 Selling Leads, Price trend, MC100E160 DataSheet download, circuit diagram from SeekIC.com

Features: • Provides Odd-HIGH Parity of 12 Inputs• Shiftable Output Register with Hold• 900ps Max. D to Q/Q Output• Enable• Asynchronous Register Reset• Dual Clocks• Extended 100E VEE Range of 4.2V to 5.46V• 75k Input Pulldown ResistorsPinoutDescri...

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MC100E160: Features: • Provides Odd-HIGH Parity of 12 Inputs• Shiftable Output Register with Hold• 900ps Max. D to Q/Q Output• Enable• Asynchronous Register Reset• Dual Cloc...

MC100E160 Data Sheet

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Part Number:: MC100E160
Supply Ability:: 5000

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Qty
1~5000

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Negotiable

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Upload time: 2024/11/27

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Product Details

Description

Features:

• Provides Odd-HIGH Parity of 12 Inputs
• Shiftable Output Register with Hold
• 900ps Max. D to Q/Q Output
• Enable
• Asynchronous Register Reset
• Dual Clocks
• Extended 100E V_EE Range of 4.2V to 5.46V
• 75k Input Pulldown Resistors

Pinout

Connection Diagram

Description

The MC100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN ) forces the Q output LOW.

The MC100E160 also features an output register. Multiplexers direct the register input, giving the option of holding present data by asserting HOLD LOW, or of shifting data in through the S-IN pin by asserting SHIFT HIGH. The output register itself is clocked by a positive edge on CLK1 or CLK2 (or both). A HIGH on the reset pin (R) overrides to force the Y output LOW.

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MC100E160

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