MB91121 Selling Leads, Price trend, MB91121 DataSheet download, circuit diagram from SeekIC.com

Features: FR CPU• 32-bit RISC, load/store architecture, 5-stage pipeline• Operating clock frequency : Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) • General purpose registers : 32 bits × 16• 16-bit fixed length instructions (basic instructions) ...

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SeekIC No. : 004413905 Detail

MB91121: Features: FR CPU• 32-bit RISC, load/store architecture, 5-stage pipeline• Operating clock frequency : Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) • Ge...

MB91121 Data Sheet

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Part Number:: MB91121
Supply Ability:: 5000

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1~5000

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Negotiable

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Upload time: 2024/11/27

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Product Details

Description

Features:

FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Operating clock frequency : Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
• General purpose registers : 32 bits × 16
• 16-bit fixed length instructions (basic instructions) , 1 instruction/1 cycle
• Memory to memory transfer, bit processing, barrel shifter processing : Optimized for embedded applications
• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems
supporting high level languages
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots : Reduced overhead time in branch executions
• Internal multiplier/supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (push PC and PS) : 6 cycles, 16 priority levels
. Bus interface
• Clock doublure : Internal 50 MHz, external bus 25 MHz operation
• 25-bit address bus (32 Mbytes memory space)
• 8/16-bit data bus
• Basic external bus cycle : 2 clock cycles
• Chip select outputs for setting down to a minimum memory block size of 64 Kbytes : 6
• Interface supported for various memory technologies
DRAM interface (area 4 and 5)
• Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area
• Unused data/address pins can be configured us input/output ports
• Little endian mode supported (Select 1 area from area 1 to 5)
. DRAM interface
• 2 banks independent control (area 4 and 5)
• Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM
• Basic bus cycle : Normally 5 cycles, 2-cycle access possible in high-speed page mode
• Programmable waveform : Automatic 1-cycle wait insertion to RAS and CAS cycles
•DRAM refresh
CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode
• Supports 8/9/10/12-bit column address width
• 2CAS/1WE, 2WE/1CAS selective
. DSP Macros (Simplified DSP)
• High-speed multiply-accumulate operation (1 machine cycle)
• Data format : 16-bit fixed-point (16 × 16 + 40 bits)
• Instruction area :    256 words × 16 bits
• Data area : 64 words × 16 bits × 1 set, 1024 words × 16 bits × 2 sets (banks)
• Capable of rounding and saturation processing
• Number of terms in addition : Up to 32 terms
• Instructions :   MAC, STR, and JMP instructions
• Delay processing :     Capable of free transfer within 32 words
• Fixed-point system :   Capable of selection from among Q12 to Q15
• Program execution control : Capable of externally selecting eight calculation programs
• Variable monitoring :      Capable of monitoring calculation results of up to 4 words without stopping the
program
• Efficient data variable areas : Two banks of data variable areas provided, enabling the CPU to execute a DSP
calculation program using one bank while accessing a data variable in the other
Cache memory
• 1 K-byte instruction cache
• 2-way set-associative configuration

Pinout

Connection Diagram

Specifications

Parameter	Symbol	Value		Unit	Remarks
Parameter	Symbol	Min.	Max.	Unit	Remarks
Power supply voltage	VCC	VSS − 0.3	VSS + 4.0	V
Analog supply voltage	AVCC	VSS − 0.3	VSS + 4.0	V	*1
Analog reference voltage	AVRH	VSS − 0.3	VSS + 4.0	V	*1
Input voltage	VI	VSS − 0.3	VCC + 0.3	V
Analog pin input voltage	VIA	VSS − 0.3	AVCC + 0.3	V
Output voltage	VO	VSS − 0.3	VCC + 0.3	V
"L" level maximum output current	IOL	-	10	mA	*2
"L" level average output current	IOLAV	-	4	mA	*3
"L" level total maximum output current	IOL	-	100	mA
"L" level total average output current	IOLAV	-	50	mA	*4
"H" level maximum output current	IOH	-	−10	mA	*2
"H" level average output current	IOHAV	-	−4	mA	*3
"H" level total maximum output current	IOH	-	−50	mA
"H" level total average output current	IOHAV	-	−20	mA	*4
Power consumption	PD	-	600	mW
Operating temperature	TA	0	+70	°C
Storage temperature	Tstg	-55	+150	°C

Description

The MB91121 is a microcontroller with a 32-bit RISC CPU (FR family *) as the core, incorporating a variety of
I/O resources, a bus control facility, and a multiplier-accumulator (simplified DSP) with internal program RAM for
built-in control applications which require advanced, high-speed CPU processing.
While being based on external bus access for supporting a vast address space accessed by the 32-bit CPU, MB91121 contains 1 K bytes of instruction cache memory and 4 K bytes of RAM (8 K bytes when the DSP is not used) for
speeding up the execution of instructions by the CPU.
In this way, MB91121 is designed for built-in applications which require high performance and processing power
of the CPU, such as digital camera, navigation system, and high-performance FAX, and printer controls.
* : FR Family stands for FUJITSU RISC controller.

MB91121

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