Features: • Clock
Built-in PLL clock frequency multiplication circuit.
Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and
multiplication of 1 to 4 times of oscillation clock(for 4 MHz oscillation clock, 4 MHz to 16 MHz).
Operation by sub clock(up to 50 kHz : 100 kHz oscillation clock divided by 2).
• 16-bit input capture (4 channels)
Detects rising, falling, or both edges.
16-bit capture register * 4
Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.
• 16-bit reload timer (2 channels)
16-bit reload timer operation (select toggle output or one-shot output)
Event count function selection provided
• Real Time watch timer (main clock)
Operates directly from oscillator clock.
Interrupt can be generated by second/minute/hour/date counter overflow.
• 16-bit PPG (3 channels)
Output pins (3 channels) , external trigger input pin (1 channel)
Output clock frequencies : fCP, fCP/22, fCP/24, fCP/26
• Delay interrupt
Generates interrupt for task switching.
Interrupts to CPU can be generated/deleted by software setting.
• External interrupts (8 channels)
8-channel independent operation
Interrupt source setting available : "L" to "H" edge/ "H" to "L" edge/ "L" level/ "H" level.
• A/D converter
10-bit or 8-bit resolution * 8 channels (input multiplexed)
Conversion time : 2.6s (at fCP = 16 MHz)
External trigger startup available (P50/INT0/ADTG)
Internal timer startup available (16-bit reload timer 1)
• UART(LIN/SCI) (2 channels)
Equipped with full duplex double buffer
Clock-asynchronous or clock-synchronous serial transfer is available
• SIO (1 channel)
Clock synchronized data transmission.
LSB-first or MSB-first data transfer selection is available.
• CAN interface
Conforms to CAN specifications version 2.0 Part A and B.
Automatic resend in case of error.
Automatic transfer in response to remote frame.
16 prioritized message buffers for data and ID
Multiple message support
Receiving filter has flexible configuration : Full bit compare/full bit mask/two partial bit masks
Supports up to 1 Mbps
CAN WAKEUP function (connects RX internally to INT0)
• LCD controller/driver (32 segment x 4 common)
Segment driver and command driver with direct LCD panel (display) drive capability
• Low voltage/Program looping detect reset
Automatic reset when low voltage is detected
Program looping detection function
• Stepping motor controller (4 channels)
High current output for each channel * 4
Synchronized 8/10-bit PWM for each channel * 2
• Sound generator
8-bit PWM signal mixed with tone frequency from 8-bit reload counter.
PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at fCP = 16 MHz)
Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)
• Input/output ports
General-purpose input/output port (CMOS output)
- 70 ports (dual clock system)
- 72 ports (single clock system)
• Input level select function for port
Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode)
• Flash memory security function
Protect the content of Flash memory (Flash memory product only)Pinout
Specifications
|
Parameter |
Symbol |
Min |
Max |
Unit |
Remarks |
| Power supply voltage*1 |
VCC |
VSS − 0.3 |
VSS + 6.0 |
V |
|
|
AVCC |
VSS − 0.3 |
VSS + 6.0 |
V |
AVCC = VCC*2 |
|
AVRH |
VSS − 0.3 |
VSS + 6.0 |
V |
AVCC AVRH*2 |
|
DVCC |
VSS − 0.3 |
VSS + 6.0 |
V |
DVCC = VCC*2 |
| Input voltage*1 |
VI |
VSS − 0.3 |
VCC + 0.3 |
V |
*3 |
| Output voltage*1 |
VO |
VSS − 0.3 |
VCC + 0.3 |
V |
|
| Maximum clamp current |
ICLAMP |
-400 |
+400 |
A |
*7 |
| Total maximum clamp current |
| ICLAMP | |
- |
4 |
mA |
*7 |
"L" level maximum
output current*4 |
IOL1 |
- |
15 |
mA |
Other than P70 to P77 and P80 to P87 |
|
IOL2 |
- |
40 |
mA |
P70 to 77 and P80 to87 |
"L" level average output
current*5 |
IOLAV1 |
- |
4 |
mA |
Other than P70 to P77 and P80 to P87 |
|
IOLAV2 |
- |
30 |
mA |
P70 to 77 and P80 to87 |
"L" level maximum
total output current |
IOL1 |
- |
100 |
mA |
Other than P70 to P77 and P80 to P87 |
|
IOL2 |
- |
330 |
mA |
P70 to 77 and P80 to87 |
"L" level average total
output current |
IOLAV1 |
- |
50 |
mA |
Other than P70 to P77 and P80 to P87 |
|
IOLAV2 |
- |
250 |
mA |
P70 to 77 and P80 to87 |
"H" level maximum
output current |
IOH1*4 |
- |
-15 |
mA |
Other than P70 to P77 and P80 to P87 |
|
IOH2*4 |
- |
-40 |
mA |
P70 to 77 and P80 to87 |
"H" level average
output current |
IOHAV1*5 |
- |
-4 |
mA |
Other than P70 to P77 and P80 to P87 |
|
IOHAV2*5 |
- |
-30 |
mA |
P70 to 77 and P80 to87 |
"H" level maximum
total output current |
IOH1 |
- |
-100 |
mA |
Other than P70 to P77 and P80 to P87 |
|
IOH2 |
- |
-330 |
mA |
P70 to 77 and P80 to87 |
"H" level average total
output current |
IOHAV1*6 |
- |
-50 |
mA |
Other than P70 to P77 and P80 to P87 |
|
IOHAV2*6 |
- |
-250 |
mA |
P70 to 77 and P80 to87 |
| Power consumption |
PD |
- |
500 |
mW |
|
| Operating temperature |
TA |
-40 |
+105 |
°C |
|
| Storage temperature |
TSTG |
-55 |
+150 |
°C |
|
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : AVCC, AVRH and DVCC shall never exceed VCC.Also, AVRH shall never exceed AVCC.
*3 : The maximum current to/from and input are limited by some means with external components, the ICLAMP rating
supersedes the VI rating.
*4 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins.
*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. The "average value" can be calculated from the formula of "operating current" times "operating factor".
*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. The "average value" can be calculated from the formula of "operating current" times " operating factor".
*7 : • Applicable to pins : P10 to P15, P50 to P57, P70 to P77, P80 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input.
DescriptionMB90925 series is a 16-bit general-purpose high-capacity microcontroller designed for vehicle meter control applications etc.
The instruction set retains the same AT architecture as F2MC-8L and F2MC-16L series, with further refinements including high-level language instructions, expanded addressing mode, enhanced signed multiplication and division computation and bit processing.
In addition, a 32-bit accumulator MB90925 is built in to enable long word processing.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
MB90925 Data Sheet
