MB81P643287-50

Features: • Double Data Rate• Bi-directional Data Strobe Signal• Eight bank operation• Burst read/write operation• Programmable burst length and CAS latency• Byte write control by DM0 to DM3• Standby Power Down Mode• 4096 Auto-refresh cycles in 32 ms...

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MB81P643287-50: Features: • Double Data Rate• Bi-directional Data Strobe Signal• Eight bank operation• Burst read/write operation• Programmable burst length and CAS latency• Byte...

floor Price/Ceiling Price

Part Number:
MB81P643287-50
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

• Double Data Rate
• Bi-directional Data Strobe Signal
• Eight bank operation
• Burst read/write operation
• Programmable burst length and CAS latency
• Byte write control by DM0 to DM3
• Standby Power Down Mode
• 4096 Auto-refresh cycles in 32 ms
• SSTL_2 (class 2) for all signals
• VDD: +2.5V Supply ± 0.2V tolerance
• VDDQ: +2.5V Supply ± 0.2V tolerance



Pinout

  Connection Diagram


Specifications

Parameter Symbol Value Unit
Voltage of VCC Supply Relative to VSS VDD, VDDQ 0.5 to +3.6 V
Voltage at Any Pin Relative to VSS VIN, VOUT 0.5 to +3.6 V
Short Circuit Output Current IOUT ±50 mA
Power Dissipation PD 2.0 W
Storage Temperature TSTG 55 to +125 °C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
                  temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.



Description

The Fujitsu MB81P643287-50 is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) with Fujitsu advanced FCRAM (Fast Cycle Random Access Memory) Core Technology, containing 67,108,864 memory cells accessible in an 32-bit format. The MB81P643287-50 features a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81P643287-50 is designed to reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timin.g constraints. The MB81P643287-50 uses Double Data Rate (DDR) where data bandwidth is twice of fast speed compared with regular SDRAMs.

The MB81P643287-50 is ideally suited for Digital Visual Systems, High Performance Graphic Adapters, Hardware Accelerators, Buffers, and other applications where large memory density and high effective bandwidth are required and where a simple interface is needed.

The MB81P643287-50 adopts new I/O interface circuitry, SSTL_2 interface, which is capable of extremely fast data transfer of quality under either terminated or point to point bus environment.




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