MAX 3000A

MAX 3000A devices are lowcost, highperformance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the 4, 5, 6, 7, and 10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and highdensity small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages.

Devices use CMOS EEPROM cells to implement logic functions. The userconfigurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations  during design development and debugging cycles, and can be programmed and erased up to 100 times.

MAX 3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmableAND/fixedOR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander and highspeed parallel expander product terms to provide up to 32 product terms per macrocell.

Devices provide programmable speed/power optimization. Speedcritical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a  nominal timing delay. MAX 3000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when nonspeedcritical signals are switching. The output drivers of all MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5V, 3.3V, and 5.0-V tolerant, allowing devices to be used in mixedvoltage systems.

MAX 3000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text-including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)-and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industrystandard PC and UNIXworkstationbased EDA tools. The software runs on Windowsbased PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations.