MAX9384

The MAX9384 fully differential dual 2:1 multiplexer (mux) features extremely low propagation delay (560ps max) and output-to-outputskew (40ps max). The MAX9384 is ideal for clock and data multiplexing applications. The two 2:1 muxes are controlled individually or simultaneously through mux select inputs COM_SEL, SEL0, and SEL1. The mux select inputs of MAX9384 are compatible with ECL/PECL logic, and are referenced to on-chip outputs VBB0 and VBB1, nominally V_CC - 1.33V.

The differential inputs D, D of MAX9384 can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip supply output V_BB as a reference voltage. All the differential inputs have bias and clamp circuits that force the outputs to a low default when the inputs are left open or at VEE. The single-ended mux select inputs of MAX9384 have pulldowns to V_EE, providing low default inputs when the select inputs are left open.

The MAX9384 operates with a wide supply range (V_CC -V_EE) of +3.0V to +5.5V for PECL or -3.0V to -5.5V for ECL, and is pin compatible with the MC100LVEL56 and MC100EL56. The MAX9384 is offered in a 20-pin wide SO package, and is specified for operation from -40to +85.