MAX9326

V_CC - V_EE.............................................................-0.3V to +4.1V
Inputs (CLK, CLK) to VEE ..........................-0.3V to (V_CC + 0.3V)
CLK to CLK ......................................................................±3.0V
Continuous Output Current .............................................50mA
Surge Output Current.....................................................100mA
VBB Sink/Source Current.............................................±0.65mA
Continuous Power Dissipation (T_A = +70)
28-Lead PLCC (derate 10.5mW/ above +70) ..........842mW
JA in Still Air ...............................................................+95/W
JC...............................................................................+25/W
28-Lead QFN (derate 20.8mW/ above +70) .........1667mW
JA in Still Air ...............................................................+48/W
JC.................................................................................+2/W
Operating Temperature Range ...........................-40 to +85
Junction Temperature......................................................+150
Storage Temperature Range .............................-65 to +150
ESD Protection
Human Body Model (CLK, CLK, Q_, Q_) .............................2kV
Soldering Temperature (10s) ..........................................+300
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The MAX9326 low-skew, 1:9 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device repeats an HSTL or LVECL/LVPECL differential input at nine differential outputs.

Outputs of MAX9326 are compatible with LVECL and LVPECL, and directly drive 50 terminated transmission lines.

The differential inputs of MAX9326 can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output voltage V_BB. All inputs have internal pulldown resistors to V_EE. The internal pulldowns and a fail-safe circuit ensure differential low default outputs when the inputs are left open or at V_EE.

The MAX9326 operates over a +2.375V to +3.8V supply range for interfacing to differential HSTL and LVPECL signals. This allows high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply.

For LVECL operation, the device operates with a -2.375V to -3.8V supply.

The MAX9326 is offered in 28-lead PLCC and spacesaving 28-lead QFN packages. The MAX9326 is specified for operation from -40 to +85.